;
; To ensure correct timing the time constant of the RC-network must 
; satisfie   512*(1/f)=-R*C*ln(1-2/5).
; For the A/D converter to operate properly, the capacitor must be  
; completly discharged between each conversion. This is done by allowing
; the discharging to take a minimum of 200us.
;
; USES:		
;	AD_L	= Low	Results
;	AD_H	= Low
;	AD_Sreg	= Low	Interrupt storage
;	AD_Flag	= Low	conversion flags
;	temp	= High	Scratch (extern) 
;	TCR_Ini = high	Prescale(extern) 
; 
; Hardware equates, constants, etc.
;
.equ	ADOUT	= PORTB
.equ	ADIN	= PINB
.equ	ADDDR	= DDRB

.equ	REYE	= PB3		; Right Eye enable
.equ	LEYE	= PB2		; Left Eye enable
.equ	CAP	= AIN0		; Charge/discharge capacitor
;.equ	CAP	= PB4		; Charge/discharge capacitor

.equ	AD_Done	= 7		; "Flags" - extern
.equ	AD_Err	= 6

.macro	Enable
	sbi	ADDDR, @0	; Set to output
	sbi	ADOUT, @0	; Drive LDR
.endmacro

.macro	Disable
	cbi	ADOUT, @0	; Set low
	cbi	ADDDR, @0	; tri-state the LDR
.endmacro

;
; Enable analog comp interrupt and set to trigger on rising edge
;
.set	ACSR_INIT= ACSR_INIT | (1<<ACIE) | (1<<ACIS1) | (1<<ACIS0)
;
; Set capacitor drive pin to output and set to 0 (default) to discharge the 
; capacitor.
;
.set	DDRB_INIT = DDRB_INIT | (1<<CAP)
;
; Timer counter set to OFF, interrupts enabled,
;
.set	TCCR0_INIT=$0
.set	TCNT0_INIT=$0		; 256 cycles to overflow
.set	TIMSK_INIT=TIMSK_INIT | (1<<TOIE0)

	.cseg

;**************************************************************************
;
; ADX_convert - Subroutine to start an A/D conversion
;
; DESCRIPTION
;	Reset conversion flag, error flag
;	Reset counter
;	Switch EYE from input (tristate) to out(0)
; 	Switch CAP from out(0) to input, no pullup
; 	Enable Timer (out control value)
; 	
AD0_conv:	Enable	REYE
		rjmp	AD_Conv

AD1_conv:	Enable	LEYE

AD_Conv:	
		clr	AD_H		; Clear MSB
		cbr	AD_Flag, (1<<AD_Done) + (1<<AD_Err)

		sbi	ACSR, ACI	; Clear any pending analog interrupt
		sbi	ACSR, ACIE	; enable analog interrupt
		
		ldi     temp,  TCNT0_INIT
		out     TCNT0, temp	; Reset counter

		cbi	ADDDR, CAP	; make input
		out     TCCR0, TCR_Ini	; start timer
 		
AD_1:		sleep
		sbrs	AD_Flag, AD_Done
		rjmp	AD_1

		Disable	REYE
		Disable	LEYE

		ret

;**************************************************************************
;
; Analog_Interrupt
;	Note:	4-11 clock latency before grabbing timer value.  Up to seven
;		cycles in Timer routine before interrupts re-enabled plus four
;		getting to the Analog interrupt handler
;
; Timer_Interrupt
;	Note:	Increment AD_H (MSB) of conversion results - enable interrupts
;		so Analog can complete while we are processing.
;
; NOTE:	temp can be clobbered between interrupt routines.  It is Ok in this case
;	since temp is used for the same thing in both routines.  If that should
;	change, then you need to make seperate temp registers... and not share
; 	them with main code or other interrupt routines.
;
Analog_Interrupt:
		in      AD_L,TCNT0	; Current count = LSB
		cbi	ACSR, ACIE	; disable interrupts
		sbi     ADDDR,CAP	; Start discharge

		sbr	AD_Flag, (1<<AD_Done)

		ldi     temp, STOP	; Stop timer0
		out     TCCR0,temp
		ldi	temp, (1<<TOV0)
		out	TIFR, temp	; reset any pending overflow

		reti                    ; Return from interrupt

Timer_Interrupt:
		sei			; enable for analog int.
		inc	AD_H
		brne	Ti1		; Overflow?

		cbi	ACSR, ACIE	; Kill analog interrupts
		sbi     ADDDR,CAP	; Start discharge
		sbi	ACSR, ACI	; reset any pending Analog interrupt

		out     TCCR0,AD_H	; AH_H = 0 = STOP Timer
		sbr	AD_Flag, (1<<AD_Done) + (1<<AD_Err)

Ti1:		ret