;
; The main tick rate is 60 khz, PWM divides that by 10
;
.equ	TICKRATE	= 60000	; 60 khz 
;
; Interrupt latency: 4 cycles + 2 for rjmp at handler + 1 for ldi + 1 for out.
; We add a fudge of 3-4 on our counter to take into account roundoff in the .set
; equation, above (based upon emperical measurements)
;
.set	TCCR0_INIT	= CLK
.set	TCNT0_INIT	= 256 - CPUCLK/TICKRATE + 5	; See note, below
.set	TIMSK_INIT	= (1<<TOIE0)

.set	CLOCK0	= 100		; further divide to 60 hz
.set	CLOCK1	= 6		; down to 10 hz
;
timer_interrupt:
	ldi	I_tmp, TCNT0_INIT
	out	TCNT0, I_tmp		; from the overflow interrupt
	in	I_save, SREG

	rcall	Analog		
	rcall	pw_control

	tst	PW_count		; divide by 10 from PWM
	brne	ti_exit			; 6 khz

	dec	Clk0			; if (--clk0 < 0)
	brge	Ti_exit			; {
	ldi	I_tmp, CLOCK0-1		; 	// Divide by 100 for 60hz
	mov	Clk0, I_tmp		;     Clk0 = CLOCK0-1
	rcall	AD_Conv

	dec	Clk1			;     if (!Clk1)
	brge	Ti_exit			;     {
	ldi	I_tmp, CLOCK1-1		; 
	mov	Clk1, I_tmp		;	  Clk1 = CLOCK1
;
; Decrement our 100ms counters here
;
	ldi	I_tmp, 0xFF
	cp	B_Delay, I_Tmp		; Don't dec if 0xFF
	breq	ti_1
	tst	B_Delay			; Dec to zero.
	breq	ti_1
	dec	B_Delay
ti_1:
	cp	E_Delay, I_Tmp		; Don't dec if 0xFF
	breq	ti_2
	tst	E_Delay
	breq	ti_2
	dec	E_Delay
ti_2:
Ti_exit:
	out	SREG, I_save
	reti