.nolist
.include "s1200def.inc"
.list
;
; Define all registers here
;
; NOTE: R13-15, R27-29, 31 free
;
; 1. Each int handler needs a high tmp and SREG save register if it is 
;	a. going to allow interrupts, or be generated while in another.
;	b. needs to diddle high I/O or load constant data.
;	c. depends upon SREG flags
; 2. This code has two handlers: Timer and Extern (UART) - neither can interrupt
;	the other, but we seperate the tmp and sreg anyway.
; 3. Counters can be moved to low register with minor code additions.
; 4. ZL is used for monitor.
;
; Main Routine Stuff
;
.def	Flags	= R16		; conversion/comm flags

.equ	AD_Done	= 7		; 
.equ	AD_Ovr	= 6		; Overflow
.equ	AD_Left	= 5		; Left/Right flag
.equ	Ar_Disable=4		; 1 = disable arbitrate process
.equ	RxRdy	= 0		; 
;
; Monitor routine stuff
;
.def	M_Temp		= R0	; Temp storage for monitor byte read/write
.def	M_Flags	= R17		; see module for bit definitions.
;
; Behavior Logic Variables
;
; The following are Bit flags that live in the upper nibble of B_State
;
.equ	B_Right	= 4		; right bumper detect
.equ	B_Bump	= 5		; In bump evasion mode
.equ	B_Left	= 6		; Left Bumper detect

.def	B_Delay		= R1	; 0=no sleep, 1-254=1/10 sec delay, 255=halt
.def	B_State	= R18
.def	E_Delay 	= R2
.def	E_State	= R19
.def	E_temp	= R20
;
; Drive commands (exclusive) live in the lower 3 bits of the state byte
;
.equ	Fd_Slow	= 1
.equ	Fd_Fast	= 2
.equ	Bk_Slow	= 3
.equ	Bk_Fast	= 4
.equ	Turn_Left= 5
.equ	Turn_Right= 6
.equ	Arc_Left= 7
.equ	Arc_Right= 8
.equ	Dr_stop	= 9
;
; Analog stuff
;
.def	AD_Results	= R3	; results 
.def	Left_eye	= R4
.def	Right_eye	= R5
;
; Usart stuff
;
.def	bitcnt	= R21		; bit counter
.def	Txbyte	= R22		; Data to be transmitted
.def	Rxbyte	= R22		; Received data
.def	U_tmp	= R24		; Baud rate counter/temp register
;
; Timer Registers
;
.def	I_save		= R7	; Storage for the SREG in interrupt routine
.def	I_tmp	= R25		; General purpose = used in interrupts only!

.def	Clk0		= R8
.def	Clk1		= R9
;
; PWM Registers
;
.def	PW_Count	= R10	; free running counter

.def	RightM	= R26		; Motor 1 level, signed
.def	LeftM	= R27		; Motor 2 level, signed
.def	hold_1		= R11	; Motor 1 holding register
.def	hold_2		= R12	; Motor 2 Holding register
;
; Enable interrupts.
;
.set	MCUCR_INIT=MCUCR_INIT | (1<<SE)	; Sleep mode = idle
.set	SREG_INIT=SREG_INIT | (1<<I)
;
; Hardware Equates
;
;.equ	CPUCLK		= 12830000	; 12.06 Mhz 
.equ	CPUCLK		= 4000000	; 4 Mhz on dev board

;
; START OF CODE SEGMENT
;
	.cseg
	.org 0

	rjmp	reset
	.org	INT0addr		; These defines take care of 
	rjmp	extern_interrupt	; shifting vectors between processors
	.org	OVF0addr
	rjmp	timer_interrupt

.include	"timer.asm"
.include	"analog.asm"
.include	"pwm.asm"
.include	"uart1200.asm"
.include	"mon1200.asm"
.include	"brains.asm"
.include	"cpu.asm"


reset:				; ONLY ONE LEVEL OF RCALL ALLOWED
	rcall	cpu_init
	rjmp	Monitor		; Initial call, returns, below, to M_Ret

forever:
	rcall	getc
	brtc	mo_ret		; Call monitor only when char available
	rjmp	Monitor		; pseudo call, to flatten stack.
mo_Ret:
	tst	B_Delay
	brne	F1
	rcall	Bump
F1:
	tst	E_Delay
	brne	f2
	rcall	Eyes
f2:
	rcall	Arbitrate

	sleep
	rjmp	forever